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Digital Asic Design Engineer Interview Questions
46 digital asic design engineer interview questions shared by candidates
Design group people are very very nice. In verification group, was asked knowledge in undergraduate school, like communication principle and analog circuit questions. I almost forgot the communication principle, but he kept on asking.... I kind of hate this guy
Technical Questions: Questions about Latch vs Flip-Flop. Draw a D-flip-Flop, linked them together to make a linear feedback shift register. Draw timing diagram. (Setup/Hold time). Draw complementary style inventor. (Pmos,Nmos). Why Pmos is on the top? talked about low power design principle. Problem solving: A problem about "Three boxes are labeled “Apples,” “Oranges,” and “Apples and Oranges.”". Google it. Write a program to find a parenthesis in a string. Ex: A(+SDF09)(u&(.
It was mainly behavior questions about resume
What are the areas of my interest?
Fifo functionality and verilog code to write
The interviewer drew two flip flops, told me the frequency of clock and input signal, and let me draw output waveform.
what is the blocking and non-blocking statement in Verilog?
Are you interested in the position
White-board diagram of a block with one input pin (+ clock), and one output pin. The input is a serial stream of data. The output =1 whenever the pattern "0110" has been seen on the serial data. Everything is synchronous to the clock input. Write the Verilog. Given the shortened time constraint for the interview, diagram the design solution. In addition to what you come up with, write a bubble diagram for an FSM solution.
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