Pipelining Hazards?
Cpu Design Engineer Interview Questions
81 cpu design engineer interview questions shared by candidates
Draw a state diagram for a given pattern. If even number if 0's come as input, then the output is asserted on every even consecutive 1. If odd number if 0's come as input, then the output is asserted on every odd consecutive 1.
Do you know anything about RISC Architecture?
Describe a situation when you would use a Direct mapped cache over a set associative cache.
What is cache
Regarding CPU Clock Signals and Timing Analysis.
compare tradeoffs of 10 wide vs. 4x 2.5 wide parallel transistors. Made me think.
What are some ways for error testing/handling in software?
Draw the layout (stick diagram) for an AND_OR circuit?
expected questions
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