(Unexpected) What the types of caches?
Senior Asic Verification Engineer Interview Questions
12 senior asic verification engineer interview questions shared by candidates
What is a parametrized class?
fork-join use in a sequence. UVM Test bench architecture. Virtual interface requirement. etc.
Difference Between Associative array and Dynamic Arrya
Related to SV + UVM + Puzzles + Perl and other scripting language
Design an arbiter. This was detailed and went on for the whole 45+ mins.
Full adder circuit, FIFO, Capacitance effect, C, Verilog
Questions asked were based on the profile and the experience
My previous experience, as well as a few mock examples related to verification and what my process would be
Call uvm_agent function from uvm_sequence to display "hello world"
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